High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

Author

Youngjoo Lee ; Hoyoung Yoo ; Injae Yoo ; In-Cheol Park

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea

Volume

22

Issue

5

fYear

2014

fDate

May-14

Firstpage

1183

Lastpage

1187

Abstract

This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed to relax the hardware complexity of a massive-parallel BCH decoder and increase the operating frequency. In a 130-nm CMOS process, a (8640, 8192, 32) BCH decoder designed as a prototype provides a decoding throughput of 6.4 Gb/s while occupying an area of 0.85 mm².

Keywords

BCH codes; CMOS digital integrated circuits; decoding; flash memories; optimisation; CMOS process; NAND flash memory applications; data sequence; decoding throughput; encoder; flash memory channel; hardware complexity; high data rate; high-throughput architecture; low-complexity BCH decoding architecture; massive-parallel decoder; operating frequency; optimizing methods; serial interface standards; size 130 nm; solid-state drives; BCH code; VLSI; VLSI.; circuit optimization; digital integrated circuits (ICs); flash memory;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2013.2264687

Filename

6545385