Title :
Performance-driven mapping for CPLD architectures
Author :
Chen, Deming ; Cong, Jason ; Ercegovac, Milos ; Huang, Zhijun
Author_Institution :
Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
Abstract :
We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLA-style logic cells. The primary objective of the algorithm is to minimize the depth of the mapped circuit. We also develop several techniques for area reduction, including threshold control of PLA fanouts and product terms, slack-time relaxation, and PLA packing. We compare PLAmap with a previous algorithm TEMPLA (Anderson and Brown 1998) and a commercial tool Altera Multiple Array MatriX (MAX) + PLUS II (Altera Corporation 2000) using Microelectronics Center of North Carolina (MCNC) benchmark circuits. With a relatively small area overhead, PLAmap reduces circuit depth by 50% compared to TEMPLA and reduces circuit delay by 48% compared to MAX + PLUS II v9.6.
Keywords :
circuit layout CAD; directed graphs; logic CAD; minimisation of switching nets; programmable logic arrays; Altera multiple array matrix; CPLD architectures; MCNC benchmark circuits; PLA fanouts; PLA packing; PLA-style logic cells; PLAmap; PLUS II; TEMPLA; area reduction; circuit delay; circuit depth; complex programmable logic device architectures; directed acyclic graph; mapped circuit depth; performance-driven mapping; product terms; programmable logic array mapping algorithm; relatively small area overhead; slack-time relaxation; technology mapping; threshold control; Computer science; Delay; Field programmable gate arrays; Integrated circuit interconnections; Logic design; Logic devices; Microelectronics; Programmable logic arrays; Programmable logic devices; Table lookup;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.818120
