DocumentCode
794140
Title
CMOS multiplier for grounded capacitors
Author
Pennisi, S.
Volume
38
Issue
15
fYear
2002
fDate
7/18/2002 12:00:00 AM
Firstpage
765
Lastpage
766
Abstract
A CMOS circuit suited particularly to magnifying the value of a grounded unit capacitor is presented. The multiplication factor is achieved through the gain of current mirrors and its maximum value is limited solely by power consumption constraints. Solutions are then developed to reduce power dissipation, to enable the detection of small unit capacitances, and to enlarge the operating frequency bandwidth
Keywords
CMOS analogue integrated circuits; analogue multipliers; capacitance measurement; capacitors; current mirrors; low-power electronics; 0.8 μm CMOS process; 0.8 micron; CMOS multiplier; analogue integrated systems; current mirrors; grounded capacitors; grounded unit capacitor value magnification; multiplication factor; operating frequency bandwidth; power consumption constraints; power dissipation; small unit capacitance detection; source-follower transistor;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20020517
Filename
1021828
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