Parasitic-aware design and optimization of a CMOS RF power amplifier

Implementation of fully integrated CMOS RF power amplifiers is a challenge owing to the low breakdown voltage of aggressively scaled CMOS transistors and parasitic effects associated with on-chip passive components. To address this problem, a parasitic-aware design and optimization paradigm and novel power amplifier circuit design techniques are proposed. The parasitic-aware synthesis described herein employs a simulated annealing algorithm that includes an adaptive tunneling mechanism and post-optimization sensitivity analysis (i.e., design centering) with respect to process, voltage, and temperature variations. Several design techniques are introduced including a self-biased power-amplifier configuration and a digitally controlled conduction angle topology. The techniques are validated via the design of a fully differential nonlinear three-stage 900-MHz GSM power amplifier integrated in 2 mm² in 250-nm CMOS that outputs 2 W (1.5 W) with 30% (43%) drain efficiency from a single 3.0-V (2.5-V) power supply.