Title :
High-speed division architecture for GF(2m)
Author :
Kim, Chang Hoon ; Hong, Chun Pyo
Author_Institution :
Dept. of Comput. & Inf. Eng., Taegu Univ., Kyungbuk, South Korea
fDate :
7/18/2002 12:00:00 AM
Abstract :
A new division architecture for GF(2m) with standard basis representation is presented. The proposed architecture is based on a modified version of the binary extended greatest common divisor algorithm; it reduces computational delay time and hardware complexity
Keywords :
Galois fields; digital arithmetic; dividing circuits; binary extended greatest common divisor algorithm; computational delay time reduction; hardware complexity reduction; high-speed division architecture; standard basis representation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20020550
