TORUS-switch: a scalable internal speed-up ATM switch architecture and its 5 Gbit/s switch LSI

Author

Genda, K. ; Yamanaka, N.

Author_Institution

NTT Network Service Syst. Lab., Tokyo, Japan

Volume

31

Issue

11

fYear

1995

fDate

5/25/1995 12:00:00 AM

Firstpage

906

Lastpage

908

Abstract

A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient

Keywords

B-ISDN; asynchronous transfer mode; bipolar digital integrated circuits; large scale integration; multimedia communication; synchronisation; telecommunication switching; 5 Gbit/s; ATM switch architecture; LSI; TORUS-switch; advanced Si-bipolar process; cell transmission; cylindrical configuration; distributed contention control; fixed output-precedence scheme; internal speed-up crosspoint switch; scalable architecture; self-bit-synchronisation technique;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:19950578

Filename

390911