Fabrication of raised S/D gate-all-around transistor and gate misalignment analysis

Author

Yin, Chunshan ; Chan, Philip C.H. ; Chan, Victor W.C.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China

Volume

24

Issue

10

fYear

2003

Firstpage

658

Lastpage

660

Abstract

In this letter, we present the implementation of a new raised source/drain (S/D) gate-all-around transistor (GAT). The device is fabricated on a bulk silicon wafer using a technique known as metal-induced-lateral-crystallization (MILC). Compared to conventional single gate MOSFETs, the GAT shows a smaller subthreshold-slope (SS), reduced drain-induced barrier lowering (DIBL), and almost doubled (187%) drive current. Gate misalignment is briefly studied using this novel device. It is found that the SS, DIBL, and drive current will degrade abruptly when gate misalignment is larger than 17% of gate length.

Keywords

MOSFET; crystallisation; silicon-on-insulator; Si; bulk silicon wafer; double-gate SOI MOSFET; drain-induced barrier lowering; drive current; fabrication process; gate misalignment analysis; metal-induced lateral crystallization; raised source/drain gate-all-around transistor; subthreshold slope; Degradation; Design optimization; Electrodes; Fabrication; MOSFETs; Monitoring; Semiconductor films; Silicon; Thickness control;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2003.817367

Filename

1233946