Title :
A unified theory for mixed CMOS/BiCMOS buffer optimization
Author :
Sakurai, Takayasu
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
7/1/1992 12:00:00 AM
Abstract :
A simple yet realistic gate sizing theory is presented to optimize delay of a cascaded gate buffer. The theory is based on the fact that CMOS/BiCMOS gate delay is linearly dependent on fan-out f, that is the delay can be expressed as Af+B, where A and B are coefficients. The optimum fan-out fOPT is shown to be approximated as e+B/1.5A for a gate chain. The theory covers various BiCMOS/CMOS gate types such as NANDs and NORs in a unified framework. The existence of spurious capacitance is shown to increase the size of all transistors compared with the case without the spurious capacitance.
Keywords :
BIMOS integrated circuits; CMOS integrated circuits; buffer circuits; cascade networks; logic gates; NANDs; NORs; buffer optimisation; cascaded gate buffer; fan-out; gate delay; gate sizing theory; mixed CMOS/BiCMOS buffer; spurious capacitance; BiCMOS integrated circuits; CMOS logic circuits; Capacitance; Delay effects; Delay lines; Design automation; Inverters; Logic devices; Logic gates; MOSFET circuits; Optimized production technology;
Journal_Title :
Solid-State Circuits, IEEE Journal of
