A floating-point cell library and a 100-Mflops image signal processor

A novel floating-point cell library for image signal processors that includes a floating-point arithmetic logic unit (ALU), a floating-point multiplier (MPY), an instruction RAM, and a data register file is considered. It has been designed for high-speed operation. An adder-subtracter and a bit alignment circuit have been developed for the ALU. As its application, a vector processor that includes two ALUs, an MPY, an instruction RAM, and a register file has been developed. The processor has a peak performance of 100 Mflops at 33 MHz. CMOS fabrication technology with a 1.0- mu m gate length was used. Other circuits used in the processor were synthesized by a logic synthesizer. To achieve high-speed operation logic synthesis and optimization technique based on implicit don´t care information in register transfer level hardware descriptions has been developed. A high-performance image signal processor has been developed using the floating-point cell library, and the logic synthesis and optimization technique.