• DocumentCode
    795253
  • Title

    Memory-controlled frequency divider for fractional-N synthesisers

  • Author

    Brennan, Paul V. ; Jiang, Dai ; Wang, Huifang

  • Author_Institution
    Dept. of Electron. & Electr. Eng., Univ. Coll. London
  • Volume
    42
  • Issue
    21
  • fYear
    2006
  • Firstpage
    1202
  • Lastpage
    1203
  • Abstract
    A new programmable frequency divider technique based on the memory-control of a prescaler is presented. It is particularly suited to FPGA or PLD implementations and for use in conjunction with stored-sequence or other fractional-N frequency synthesiser architectures
  • Keywords
    field programmable gate arrays; frequency dividers; frequency synthesizers; prescalers; programmable logic devices; FPGA implementations; PLD implementations; fractional-N synthesisers; memory-controlled frequency divider; prescalers; programmable frequency divider;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • Filename
    1715181
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=795253