Analog neural programmable optimizers in CMOS VLSI technologies

Author

Domínguez-Castro, R. ; Rodríguez-Vázquez, A. ; Huertas, J.L. ; Sánchez-Sinencio, E.

Author_Institution

Dept. of Design of Analog Circuits, Seville Univ., Spain

Volume

27

Issue

7

fYear

1992

fDate

7/1/1992 12:00:00 AM

Firstpage

1110

Lastpage

1115

Abstract

Introduces a parallel switched-capacitor (SC) neural optimizer architecture and discusses area limitations due to the incorporation of programmability issues. Due to these limitations this architecture is only suitable for low dimension problems. A serial time-multiplexed architecture which allows digital control on the weight values with reasonable area figures is presented. A 3- mu m CMOS SC prototype demonstrating the concept of SC analog neural optimizers via an integrated circuit is discussed.

Keywords

CMOS integrated circuits; VLSI; neural nets; switched capacitor networks; 3 micron; CMOS SC prototype; CMOS VLSI technologies; SC analog neural optimizers; area limitations; digital control; low dimension problems; neural optimizer architecture; programmability; serial time-multiplexed architecture; weight values; Analog integrated circuits; CMOS analog integrated circuits; CMOS integrated circuits; CMOS technology; Constraint optimization; Cost function; Digital control; Helium; Mathematical model; Prototypes; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.142611

Filename

142611