A high-speed CMOS circuit for 1.2-Gb/s 16*16 ATM switching

Author

Chemarin, Alain ; André, Alain ; Botta, Alain ; Majos, Jacques ; Rainard, Jean-Luc ; Teyssier, Henri ; Thorel, Pierre

Author_Institution

CNET, Meylan, France

Volume

27

Issue

7

fYear

1992

fDate

7/1/1992 12:00:00 AM

Firstpage

1116

Lastpage

1120

Abstract

The authors describe a 0.7- mu m CMOS asynchronous transfer mode (ATM) switch circuit of 350 K transistors, the kernel of a fully autonomous 16*16 ATM switching matrix devoted to telecommunications. This matrix is able to switch ATM multiplexes with a throughput of up to 1.2 Gb/s per access line, and was implemented using 16 receiver/transmitter circuits and a control circuit. The architecture of the ATM switch circuit is based on a large embedded and shared dual-access memory. Each chip processes 4-b slices of each incoming multiplex. Seven such chips working in parallel are enough to achieve standard ATM cell switching. Up-to-date test features, such as boundary scan, built-in self-test, and redundancy were implemented in the circuit.

Keywords

CMOS integrated circuits; built-in self test; multiplexing equipment; time division multiplexing; 0.7 micron; 1.2 Gbit/s; ATM switching; asynchronous transfer mode; boundary scan; built-in self-test; dual-access memory; high-speed CMOS circuit; multiplexes; redundancy; switch circuit; telecommunications; throughput; Asynchronous transfer mode; Automatic testing; Circuit testing; Kernel; Switches; Switching circuits; Telecommunication control; Telecommunication switching; Throughput; Transmitters;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.142612

Filename

142612