DocumentCode :
795501
Title :
Contention-conscious transaction ordering in multiprocessor DSP systems
Author :
Khandelia, Mukul ; Bambha, Neal K. ; Bhattacharyya, Shuvra S.
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
Volume :
54
Issue :
2
fYear :
2006
Firstpage :
556
Lastpage :
569
Abstract :
This paper explores the problem of efficiently ordering interprocessor communication (IPC) operations in statically scheduled multiprocessors for iterative dataflow graphs. In most digital signal processing (DSP) applications, the throughput of the system is significantly affected by communication costs. By explicitly modeling these costs within an effective graph-theoretic analysis framework, we show that ordered transaction schedules can significantly outperform self-timed schedules even when synchronization costs are low. However, we also show that when communication latencies are nonnegligible, finding an optimal transaction order given a static schedule is an NP-complete problem, and that this intractability holds both under iterative and noniterative execution. We develop new heuristics for finding efficient transaction orders, and perform an extensive experimental comparison to gauge the performance of these heuristics.
Keywords :
data flow graphs; iterative methods; message passing; processor scheduling; signal processing; contention-conscious transaction ordering; digital signal processing; graph-theoretic analysis; interprocessor communication; iterative dataflow graphs; iterative methods; multiprocessor DSP systems; Costs; Delay; Digital signal processing; Digital signal processing chips; Embedded system; Instruments; Internet telephony; NP-complete problem; Processor scheduling; Throughput; Dataflow; multiprocessor; scheduling; synchronization;
fLanguage :
English
Journal_Title :
Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1053-587X
Type :
jour
DOI :
10.1109/TSP.2005.861074
Filename :
1576984
Link To Document :
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