Scaling, subthreshold, and leakage current matching characteristics in high-temperature (25°C-250°C) VLSI CMOS devices

The effects of CMOS technology scaling on the high-temperature (25-250°C) characteristics of the threshold voltage, the channel mobility, and drain and source-to-body leakage currents are presented. Three versions (6-, 4-, and 2-μm minimum feature length) of a standard CMOS process optimized for digital circuit applications, and a 4-μm version of the same process optimized for analog circuit applications are compared with respect to the aforementioned parameters. The temperature-induced trends are qualitatively similar for the four technologies. A dramatic increase in the subthreshold parameter is observed above 150°C in the analog process, which is consistent with the previously reported onset of diffusion-leakage currents near this temperature. Detailed leakage-current matching measurements are shown to lead to severe resolution-speed tradeoffs in the design of sampled data circuits operated at elevated temperatures. A simple capacitor switched by a CMOS transmission gate is used to illustrate the latter considerations. Silicon CMOS technologies built on low-resistance epitaxial layers, combined with gold-based metallizations, are found to be the most promising among existing technologies for applications up to 250°C. Specific needs for further research on the severe-environment behavior of state-of-the-art and emerging technologies are discussed