DocumentCode :
795663
Title :
Petri net modeling of gate and interconnect delays for power estimation
Author :
Murugavel, Ashok K. ; Ranganathan, Nagarajan
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Volume :
11
Issue :
5
fYear :
2003
Firstpage :
921
Lastpage :
927
Abstract :
Switching activity estimation is an important step in average power estimation of VLSI circuits at the gate level. In this paper, we present a novel approach based on Petri net modeling for real delay switching activity and power estimation of CMOS circuits, considering both gate and interconnect delays. We propose a new type of Petri net called hierarchical colored hardware Petri net (HCHPN), which accurately captures the spatial and temporal correlations in modeling switching activity. The logic circuit is first modeled as a gate signal graph (GSG) which is then converted into the corresponding HCHPN and simulated as a Petri net to obtain the switching activity estimates and the power values. The proposed method is accurate and fast compared to other simulative methods. Experimental results are provided for ISCAS ´85 and ISCAS ´89 benchmark circuits and compared with the commercial tools, PowerMill, and Prime Power.
Keywords :
CMOS logic circuits; Petri nets; VLSI; delays; integrated circuit modelling; CMOS circuit; Petri net model; VLSI circuit; gate delay; gate signal graph; hierarchical colored hardware Petri net; interconnect delay; logic circuit; power estimation; switching activity; Circuit simulation; Delay estimation; Hardware; IEEE activities; Integrated circuit interconnections; Petri nets; Power system modeling; Semiconductor device modeling; Switching circuits; Very large scale integration;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2003.817110
Filename :
1234411
Link To Document :
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