Monolithic digital galvanic isolation buffer fabricated in silicon on sapphire CMOS

Author

Culurciello, E. ; Pouliquen, P.O. ; Andreou, A.G. ; Strohbehn, K. ; Jaskulek, S.

Author_Institution

Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA

Volume

41

Issue

9

fYear

2005

fDate

4/28/2005 12:00:00 AM

Firstpage

526

Lastpage

528

Abstract

A monolithic four-channel digital galvanic isolation buffer in the 0.5 μm silicon on sapphire (SOS) CMOS technology is reported. Advantage is taken of the insulating properties of the sapphire substrate to integrate on the same die both the isolation structure and the interface electronics. Each isolation channel has been tested to operate at data rates over 100 Mbit/s. The system can tolerate ground bounces of 1 V/μs and is tested for 800 V isolation. The system includes an integrated isolation charge pump to power the input circuit and is hence capable of operating from a single 3.3 V power supply.

Keywords

CMOS digital integrated circuits; buffer circuits; elemental semiconductors; isolation technology; monolithic integrated circuits; sapphire; silicon; 0.5 micron; 3.3 V; 800 V; CMOS technology; Si; data rate; four-channel digital galvanic isolation buffer; ground bounce; insulating properties; integrated isolation charge pump; interface electronics; isolation channel; monolithic buffer; silicon on sapphire;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:20050006

Filename

1426563