An ECL to CMOS level converter with complementary bipolar output stage

Author

Rau, Martin ; Pfleidere, Hans-Jörg

Author_Institution

Dept. of Electr. Eng., Ulm Univ., Germany

Volume

30

Issue

7

fYear

1995

fDate

7/1/1995 12:00:00 AM

Firstpage

781

Lastpage

787

Abstract

A novel circuit scheme for the fast amplification of digital signals is presented. A fully complementary bipolar output stage realizes small delay and steep output signal slopes. The improved performance is achieved by intentionally saturating the bipolar output transistors, which allows one to supply the maximum current to the output. We evaluate the performance of saturated bipolar transistors fabricated on bulk silicon. Compared to known circuit schemes, the proposed circuit shows significantly reduced total delay and power dissipation. The driving capability for large capacitive loads is improved. Samples produced in a 2 μm-BiCMOS technology verify the simulated performance

Keywords

BiCMOS digital integrated circuits; BiCMOS logic circuits; convertors; delays; digital signals; emitter-coupled logic; 2 micron; BiCMOS technology; ECL to CMOS level converter; bipolar output transistor saturation; digital signal amplification; driving capability; fully complementary bipolar output stage; large capacitive loads; output signal slopes; power dissipation; total delay; BiCMOS integrated circuits; Bipolar transistors; CMOS logic circuits; CMOS technology; Circuit simulation; Current supplies; Delay; Power dissipation; Silicon; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.391117

Filename

391117