Title :
A testable design of logic circuits under highly observable condition
Author :
Xiaoqing, Wen ; Kinoshita, Kozo
Author_Institution :
Dept. of Appl. Phys., Osaka Univ., Japan
fDate :
5/1/1992 12:00:00 AM
Abstract :
The concept of k-UCP circuits is proposed. In a k-UCP circuit, all stuck-at faults and stuck-open faults can be detected and located by k+1 and k(k+1)+1 tests, respectively, under the highly observable condition. A method of modifying an arbitrary combinational circuit into a k-UCP circuit is also proposed
Keywords :
combinatorial circuits; fault tolerant computing; integrated circuit testing; integrated logic circuits; logic testing; combinational circuit; highly observable condition; logic circuits; stuck-at faults; stuck-open faults; testable design; Circuit faults; Circuit testing; Combinational circuits; Controllability; Electrical fault detection; Electron beams; Fault detection; Inverters; Logic circuits; Logic testing;
Journal_Title :
Computers, IEEE Transactions on
