Design concept for radiation hardening of low power and low voltage dynamic memories

Author

Schleifer, Horst ; Ropp, Thomas V d ; Hoffmann, Kurt ; Reczek, Werner

Author_Institution

Semicond. Group, Memory Div., Siemens AG, Munich, Germany

Volume

30

Issue

7

fYear

1995

fDate

7/1/1995 12:00:00 AM

Firstpage

826

Lastpage

829

Abstract

A radiation hard low power, low voltage dynamic memory is obtained by the use of a dummy cell concept. Compared to conventional dummy cell concepts, this concept applies a fully sized dummy cell. By optimizing the dummy cell precharge voltage for 5 V and 3 V operation and the timing of the dummy word-line, the overall soft error rate (SER) of the chip is improved by 2 orders of magnitude. An additional improvement of 1 order of magnitude is possible for 3 V operation by adjusting substrate bias and cell plate voltage. The results are verified by an accelerated SER measurement with a radium 226 source and an additional field soft error study

Keywords

DRAM chips; integrated circuit design; integrated circuit testing; radiation hardening (electronics); 3 V; 5 V; DRAMs; accelerated SER measurement; cell plate voltage; dummy cell concept; dummy word-line; dynamic memories; field soft error study; precharge voltage; radiation hardening; soft error rate; substrate bias; Acceleration; Capacitance; Costs; Error analysis; Life estimation; Low voltage; Packaging; Radiation hardening; System testing; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.391125

Filename

391125