Calculation of the soft error rate of submicron CMOS logic circuits

Author

Juhnke, T. ; Klar, H.

Author_Institution

Inst. of Microelectron., Tech. Univ. Berlin, Germany

Volume

30

Issue

7

fYear

1995

fDate

7/1/1995 12:00:00 AM

Firstpage

830

Lastpage

834

Abstract

A method to calculate the soft error rate (SER) of CMOS logic circuits with dynamic pipeline registers is described. This method takes into account charge collection by drift and diffusion. The method is verified by comparison of calculated SER´s to measurement results. Using this method, the SER of a highly pipelined multiplier is calculated as a function of supply voltage for a 0.6 μm, 0.3 μm, and 0.12 μm technology, respectively. It has been found that the SER of such highly pipelined submicron CMOS circuits may become too high so that countermeasures have to be taken. Since the SER greatly increases with decreasing supply voltage, low-power/low-voltage circuits may show more than eight times the SER for half the normal supply voltage as compared to conventional designs

Keywords

CMOS logic circuits; logic testing; multiplying circuits; pipeline arithmetic; 0.12 to 0.6 micron; SER; charge collection; dynamic pipeline registers; low-power/low-voltage circuits; soft error rate; submicron CMOS logic circuits; supply voltage; CMOS logic circuits; CMOS technology; Circuit simulation; Error analysis; Geometry; Logic circuits; MOS devices; Pipelines; Registers; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.391126

Filename

391126