DocumentCode
796866
Title
DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals
Author
Golander, Amit ; Weiss, Shlomo ; Ronen, Ronny
Author_Institution
Tel Aviv Univ., Tel Aviv
Volume
7
Issue
2
fYear
2008
Firstpage
65
Lastpage
68
Abstract
DMR (dual modular redundancy) was suggested for increasing reliability. Classical DMR consists of pairs of cores that check each other and are pre-connected during manufacturing by dedicated links. In this paper we introduce the dynamic dual modular redundancy (DDMR) architecture. DDMR supports run-time scheduling of redundant threads, which has significant benefits relative to static binding. To allow dynamic pairing, DDMR replaces the special links with a novel ring architecture. DDMR uses short instruction sequences for validation, smaller than the processor reorder buffer. Such short sequences reduce latencies in parallel programs and save resources needed to buffer uncommitted data. DDMR scales with the number of cores and may be used in large multicore architectures.
Keywords
buffer storage; parallel architectures; processor scheduling; DDMR; dynamic dual modular redundancy; multicore architectures; parallel programs; processor reorder buffer; ring architecture; run-time scheduling; scalable dual modular redundancy; short validation intervals; Multi-core/single-chip multiprocessors; Redundant design;
fLanguage
English
Journal_Title
Computer Architecture Letters
Publisher
ieee
ISSN
1556-6056
Type
jour
DOI
10.1109/L-CA.2008.12
Filename
4564436
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