Counter-based compaction: Delay and stuck-open faults

In this paper, we study the properties of all major counter-based compaction schemes when the circuit under test is affected by delay or stuck-open faults. We present an error model that accurately describes the behavior of such circuits. The error model inherits from the asymmetric error model. Using this model, we compute exact aliasing probability for any test session length; we also determine the asymptotic aliasing probability. Examples that compare aliasing in counter-based compaction with aliasing in LFSRs indicate that the latter is more “predictable”