Title :
The SCC BJT: a high-performance bipolar transistor compatible with high-density deep-submicrometer BiCMOS SRAM technologies
Author :
Taft, R.C. ; Lage, C.S. ; Hayden, J.D. ; Kirsch, H.C. ; Lin, J.-H. ; Denning, D.J. ; Shapiro, F.B. ; Bockelman, D.E. ; Camilleri, N.
Author_Institution :
East Coast Labs., Salem, NY, USA
fDate :
7/1/1995 12:00:00 AM
Abstract :
We present the process development and device characterization of the Selectively Compensated Collector (SCC) BJT specifically designed for high-density deep-submicrometer BiCMOS SRAM technologies. This double-poly BJT takes advantage of the self-aligned polysilicon layers of the SRAM bit cell to obtain high performance without adding excessive process complexity. Furthermore, although an NPN device, the SCC BJT is formed in a lightly doped p-well in which the collector is formed with a single 370 keV phosphorus implant to minimize parasitic junction capacitances without the use of trench isolation or recessed oxides. The suitability of this bipolar structure outside of its original FSRAM intent is proven with its potential for bipolar logic and mixed-mode RF applications. ECL delays of 50 ps at 200 μA and a CML power-delay product of 4.5 fJ at 1.1 V supply were obtained. A 900 MHz noise figure as low as 0.54 dB at 0.5 mA with an associated gain of 14.7 dB was demonstrated as well as a dual modulus ÷4/5 prescaler operating up to 3.3 GHz for a switch current of 200 μA
Keywords :
BiCMOS logic circuits; BiCMOS memory circuits; SRAM chips; bipolar transistors; current-mode logic; emitter-coupled logic; integrated circuit technology; ion implantation; 0.5 mA; 0.54 dB; 1.1 V; 14.7 dB; 200 muA; 3.3 GHz; 370 keV; 50 ps; 900 MHz; BiCMOS SRAM; CML power-delay product; ECL delays; NPN device; P implant; SCC BJT; SRAM bit cell; Si:P; bipolar logic; deep-submicrometer BiCMOS; device characterization; double-poly BJT; dual modulus prescaler; high-density SRAM technologies; high-performance bipolar transistor; lightly doped p-well; mixed-mode RF applications; parasitic junction capacitance minimisation; process development; selectively compensated collector BJT; self-aligned polysilicon layers; BiCMOS integrated circuits; Bipolar transistors; Delay; Implants; Logic; Noise figure; Parasitic capacitance; Radio frequency; Random access memory; Switches;
Journal_Title :
Electron Devices, IEEE Transactions on
