Thermal simulation of thin-film interconnect failure caused by high current pulses

We have performed a quantitative analysis of the time-dependent temperature distributions in response to a high current pulse for very large scale integrated (VLSI) metallization structures, especially for those used in field-programmable gate array (FPGA) devices with voltage programmable links (VPL´s). Simulation results are presented as pulse width versus maximum allowed current density through Al interconnects and as visualizations of the transient temperature distributions. The adiabatic approximation for modeling the current-induced heating is found to be valid only for an extremely short pulse duration (<10^-8 sec). The thermal capacity of passivation materials can effectively inhibit the rate of temperature rise in the interconnects before the thermal equilibrium is established. As a result, the instantaneous maximum current density is largely increased particularly when a passivation material with high thermal conductivity is used