• DocumentCode
    797819
  • Title

    Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization

  • Author

    Li, Hang ; Fan, Jeffrey ; Qi, Zhenyu ; Tan, Sheldon X D ; Wu, Lifeng ; Cai, Yici ; Hong, Xianlong

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Riverside, CA
  • Volume
    25
  • Issue
    11
  • fYear
    2006
  • Firstpage
    2402
  • Lastpage
    2412
  • Abstract
    This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today´s very large scale integration physical design. The new method is based on a sensitivity-based conjugate gradient (CG) approach. But several new techniques that significantly improve the efficiency of the optimization process were adopted. First, an efficient search step scheme to replace the time-consuming line search phase in the conventional CG method for decap budget optimization was proposed. Second, instead of optimizing an entire large circuit, the circuit is partitioned into a number of smaller subcircuits and optimized separately by exploiting the locality of adding decaps. Third, the time-domain merged adjoint method was applied to compute the sensitivity information and show that the partitioning-based merged adjoint method leads to better results than the flat merged adjoint method with the improved search scheme. Experimental results show that the proposed algorithm achieves at least ten times speed-up over similar decap allocation methods reported so far with similar budget quality, and a power grid circuit with about one million nodes can be optimized using the new method in half an hour on the latest Linux workstations
  • Keywords
    VLSI; capacitors; circuit optimisation; conjugate gradient methods; logic partitioning; Linux workstations; capacitor budgeting; capacitor minimization; de-cap estimation; decap allocation; decap budget optimization; decoupling capacitor; logic partitioning; on-chip decoupling; on-chip power/grid networks; power grid circuit; sensitivity-based conjugate gradient; very large scale integration; Algorithm design and analysis; Capacitance; Capacitors; Character generation; Circuits; Minimization methods; Optimization methods; Partitioning algorithms; Time domain analysis; Very large scale integration; Decoupling capacitor; on-chip power/grid networks;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2006.870862
  • Filename
    1715425