• DocumentCode
    797886
  • Title

    An Integrated High-Level On-Line Test Synthesis Tool

  • Author

    Oikonomakos, Petros ; Zwolinski, Mark

  • Author_Institution
    Sch. of Electron. & Comput. Sci., Southampton Univ.
  • Volume
    25
  • Issue
    11
  • fYear
    2006
  • Firstpage
    2479
  • Lastpage
    2491
  • Abstract
    Several researchers have recently implemented on-line testability in the form of duplication-based self-checking digital system design, early in the design process. The authors consider the on-line testability within the optimization phase of iterative, cost function-driven high-level synthesis, such that self-checking resources are inserted automatically without any modification of the source behavioral hardware description language code. This is enabled by introducing a metric for the on-line testability. A new variation of duplication (namely inversion testing) is also proposed and used, providing the system with an additional degree of freedom for minimizing hardware overheads associated with test resource insertion. Considering the on-line testability within the synthesis process facilitates fast and painless design space exploration, resulting in a versatile high-level-synthesis process, capable of producing alternative realizations according to the designer´s directions, for alternative target technologies. Finally, the fault escape probability of the overall scheme is discussed theoretically and evaluated experimentally
  • Keywords
    automatic test equipment; design for testability; high level synthesis; data-flow synthesis; design for testability; hardware description language code; hardware overheads; high-level test synthesis tool; integrated test synthesis tool; online test synthesis tool; self-checking digital system design; self-checking resources; space exploration; Adders; Automatic testing; Circuit faults; Circuit testing; Computer science; Design automation; Digital systems; Hardware; High level synthesis; System testing; Data-flow synthesis; design for testability; high level synthesis; test synthesis;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2006.882120
  • Filename
    1715431