DocumentCode
798271
Title
A Short-Channel SOI RF Power LDMOS Technology With 
Salicide on Dual Sidewalls With Cutoff Frequency 
Author
Yang, Rong ; Li, J.F. ; Qian, H. ; Lo, G.Q. ; Balasubramanian, N. ; Kwong, D.L.
Author_Institution
Inst. of Microelectron., Singapore
Volume
27
Issue
11
fYear
2006
Firstpage
917
Lastpage
919
Abstract
In this letter, a CMOS-compatible silicon-on-insulator (SOI) RF laterally diffused MOS (LDMOS) technology is proposed based on TiSi2 salicide with SiO2/Si3N4 dual sidewalls. The use of dual sidewalls yields a large process margin for defining drift regions and preventing source-gate silicide bridging. This technology improves the cutoff frequencies and the maximum oscillation frequencies by 27%-42% and 14%-22%, respectively, for a gate length in the range of 0.5-0.25 mum. For the shortest 0.25-mum gate length, a record cutoff frequency of 19.3 GHz and a high breakdown voltage of 16.3 V are achieved simultaneously for SOI RF LDMOS. This LDMOS technology is suitable for 3.6-V-supply 0-3-GHz power RFIC applications
Keywords
microwave field effect transistors; power MOSFET; silicon compounds; silicon-on-insulator; titanium compounds; 0 to 3 GHz; 0.5 to 0.25 micron; 16.3 V; 19.3 GHz; 3.6 V; CMOS; RF laterally diffused MOS technology; SiO2-Si3N4; TiSi2; power RFIC; salicide; silicon-on-insulator; source-gate silicide bridging; CMOS technology; Cutoff frequency; Electric breakdown; Etching; Isolation technology; Microelectronics; Radio frequency; Radiofrequency integrated circuits; Silicides; Voltage; Breakdown voltage (BV); RF; cutoff frequency; laterally diffused MOS (LDMOS); maximum oscillation frequency; salicide;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2006.883561
Filename
1715466
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