Study of the electrical performance of chip-on-board (COB) devices

When a bare die is flipped directly onto the printed circuit board (PCB) during chip-on-board assembly, it becomes exposed to a number of factors, which could influence its electrical performance. Although the mechanical integrity of flip-chip devices has been thoroughly studied, there is very little evidence of detailed investigations of the electrical performance of these devices. The present paper aims to bridge this gap by studying the electrical parameters of flip chip devices and analysing the changes occurring following assembly. A dedicated test chip comprised of passive and active semiconductor devices was designed for the study. Two different types of tacky flux and underfill materials were used in the flip chip assembly process. The flip chip structures were then subjected to various environmental stress techniques for accelerating ageing. Electrical parameters of the devices such as threshold voltage, I-V characteristics, off-state leakage current, current gain, and resistance were measured at various stages of the programme. A slight change in device parameters was observed immediately after assembly. Further change in some device parameters was observed after environmental stressing. The paper investigates the mechanisms that could be responsible for the changes, such as mechanical stresses introduced during the flip chip process or ionic contamination inherent to the assembly process.