DocumentCode
799066
Title
Designing multioperand modular adders
Author
Alia, G. ; Martinelli, E.
Author_Institution
Dipartimento di Ingegneria dell´´Inf., Pisa Univ., Italy
Volume
32
Issue
1
fYear
1996
fDate
1/4/1996 12:00:00 AM
Firstpage
22
Lastpage
23
Abstract
The problem of designing efficient multioperand modular adders is approached. A carry-save adder tree is used allowing a response time lower than values in the literature, without restrictions regarding modules. Moreover it is shown that a structure such as the proposed one is suitable for evaluating |X|m within a logarithmic time
Keywords
adders; logic design; residue number systems; carry-save adder tree; design; logarithmic time; multioperand modular adders; response time;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19960026
Filename
490704
Link To Document