DocumentCode
80049
Title
Novel FPGA Implementation of Hand Sign Recognition System With SOM–Hebb Classifier
Author
Hikawa, Hiroomi ; Kaida, Keishi
Author_Institution
Grad. Sch. of Sci. & Eng., Kansai Univ., Suita, Japan
Volume
25
Issue
1
fYear
2015
fDate
Jan. 2015
Firstpage
153
Lastpage
166
Abstract
This paper proposes a hardware posture recognition system with a hybrid network. The hybrid network consists of self-organizing map (SOM) and Hebbian network. Feature vectors are extracted from input posture images, which are mapped to a lower dimensional map of neurons in the SOM. The Hebbian network is a single-layer feedforward neural network trained with a Hebbian learning algorithm to identify categories. The recognition algorithm is robust to the change in location of hand signs, but it is not immune to rotation or scaling. Its robustness to rotation and scaling was improved by adding perturbation to the training data for the SOM-Hebb classifier. In addition, neuron culling is proposed to improve performance. The whole system is implemented on a field-programmable gate array employing novel video processing architecture. The system was designed to recognize 24 American sign language hand signs, and its feasibility was verified through both simulations and experiments. The experimental results revealed that the system could accomplish recognition at a speed of 60 frames/s, while achieving an accuracy of 97.1%. Due to a novel hardware implementation, the circuit size of the proposed system is very small, which is highly suitable for embedded applications.
Keywords
Hebbian learning; field programmable gate arrays; image classification; object recognition; self-organising feature maps; video signal processing; American sign language hand signs; FPGA implementation; Hebbian learning algorithm; Hebbian network; SOM-Hebb classifier; embedded application; feature vector extraction; hand sign recognition system; hardware posture recognition system; neuron culling; self-organizing feature maps; single-layer feedforward neural network; video processing architecture; Feature extraction; Field programmable gate arrays; Gesture recognition; Hardware; Histograms; Neurons; Vectors; Field-programmable gate array (FPGA); Hebb learning; hand sign recognition; hardware; self-organizing map (SOM);
fLanguage
English
Journal_Title
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher
ieee
ISSN
1051-8215
Type
jour
DOI
10.1109/TCSVT.2014.2335831
Filename
6848809
Link To Document