Modelling of multilayer on-chip transformers

An analytical model has been proposed for multilayer stacked on-chip transformers, including the effects of the eddy current losses in the metal layers and Si substrate. The model gives good agreement with S-parameter measurements on structures fabricated using a four-metal-layer 0.35 mum CMOS process. It is shown that proper account of the eddy current losses is necessary to predict accurately the S-parameter characteristics of on-chip transformers at higher frequencies