Study of Subharmonically Injection-Locked PLLs

Author

Lee, Jri ; Wang, Huaide

Author_Institution

Electr. Eng. Dept., Nat. Taiwan Univ., Taipei

Volume

44

Issue

5

fYear

2009

fDate

5/1/2009 12:00:00 AM

Firstpage

1539

Lastpage

1553

Abstract

A complete analysis on subharmonically injection-locked PLLs develops fundamental theory for subharmonic locking phenomenon. It explains the noise shaping phenomenon, locking range and behavior, PVT tolerance, and pseudo locking issue. All of the analyses are verified by real chip measurements. Two 20-GHz PLLs based on the proposed theory are designed and fabricated in 90-nm CMOS technology to demonstrate the superiority and robustness of this technique. The first chip aims at low-noise/low-power/high-divide-ratio design, achieving 149-fs rms jitter (integrated from 100 Hz to 1 GHz) while consuming 38 mW from a 1.3-V supply. The second prototype shoots for the lowest noise performance, presenting 85-fs rms jitter (the same integration interval) with a power dissipation of 105 mW. The jitter generation (from 50 kHz to 80 MHz) measures 48 fs, which is at least twice as small as that of any other known circuits.

Keywords

CMOS integrated circuits; phase locked loops; phase noise; timing jitter; CMOS technology; chip measurements; frequency 100 Hz to 1 GHz; frequency 20 GHz; frequency 50 kHz to 80 MHz; low-noise-low-power-high-divide-ratio design; noise shaping phenomenon; power 38 mW; power dissipation; rms jitter; size 90 nm; subharmonically injection-locked PLLs; time 149 fs; time 48 fs; time 85 fs; voltage 1.3 V; Bandwidth; CMOS technology; Clocks; Frequency; Jitter; Noise shaping; Optical noise; Phase locked loops; Phase noise; Voltage-controlled oscillators; Injection locking; phase noise; phase-locked loop (PLL); rms jitter; subharmonic locking;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2009.2016701

Filename

4907332