• DocumentCode
    801795
  • Title

    Low-density Parity-check codes with run length limited (RLL) constraints

  • Author

    Li, Zongwang ; Kumar, B. V K Vijaya

  • Author_Institution
    Data Storage Syst. Center, Carnegie Mellon Univ., Pittsburgh, PA, USA
  • Volume
    42
  • Issue
    2
  • fYear
    2006
  • Firstpage
    344
  • Lastpage
    349
  • Abstract
    This paper addresses a new scheme by Vasic and Pedagani to combine low-density parity-check (LDPC) codes with run length limited (RLL) constraints. In this method, the RLL constraints are embedded into the LDPC codewords by deliberately flipping the bits of LDPC codewords that violate the RLL constraints. It is important to keep the number of flipped bits small in order to not overburden the LDPC decoder. In this paper, we introduce a method to control the number of flipped bits by using pseudorandom sequences. We present a new low-complexity iterative decoding and detection scheme to correct both the flipped bits and channel errors in a partial response channel. Analyses and simulation results show that the proposed method has good performance and reasonable complexity for (0,k) RLL constraints.
  • Keywords
    computational complexity; iterative decoding; modulation coding; parity check codes; random codes; random sequences; runlength codes; LDPC codewords; LDPC decoder; channel errors; flipped bits; low-complexity iterative decoding; low-density parity-check codes; modulation codes; partial response channel; pseudorandom sequences; run length limited constraints; AWGN; Data storage systems; Error correction; Error correction codes; Interference constraints; Iterative decoding; Modulation coding; Parity check codes; Partial response channels; Random sequences; EPR4; LDPC codes; RLL; modulation codes;
  • fLanguage
    English
  • Journal_Title
    Magnetics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9464
  • Type

    jour

  • DOI
    10.1109/TMAG.2005.861044
  • Filename
    1580704