Title :
An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices
Author :
Wang, Chao-Ching ; Cheng, Chieh-Jen ; Chen, Tien-Fu ; Wang, Jinn-Shyan
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chiayi
fDate :
5/1/2009 12:00:00 AM
Abstract :
Network security for mobile devices is in high demand because of the increasing virus count. Since mobile devices have limited CPU power, dedicated hardware is essential to provide sufficient virus detection performance. A TCAM-based virus-detection unit provides high throughput, but also challenges for low power and low cost. In this paper, an adaptively dividable dual-port BiTCAM (unifying binary and ternary CAMs) is proposed to achieve a high-throughput, low-power, and low-cost virus-detection processor for mobile devices. The proposed dual-port BiTCAM is realized with the dual-port AND-type match-line scheme which is composed of dual-port dynamic AND gates. The dual-port designs reduce power consumption and increase storage efficiency due to shared storage spaces. In addition, the dividable BiTCAM provides high flexibility for regularly updating the virus-database. The BiTCAM achieves a 48% power reduction and a 40% transistor count reduction compared with the design using a conventional single-port TCAM. The implemented 0.13 mum processor performs up to 3 Gbps virus detection with an energy consumption of 0.44 fJ/pattern-byte/scan at peak throughput.
Keywords :
associative processing; content-addressable storage; logic gates; mobile communication; telecommunication security; AND gates; AND-type match-line scheme; adaptively dividable BiTCAM; associative memories; bit rate 3 Gbit/s; content-addressable memory; dual-port BiTCAM; mobile devices; network security; shared storage spaces; transistor count reduction; virus-detection processors; CADCAM; Cams; Chaos; Computer aided manufacturing; Costs; Energy consumption; Hardware; Pattern matching; Security; Throughput; Associative memories; ClamAV; PF-CDPD; Snort; content-addressable memory; dual-port match line; high speed; low power; pattern matching; pseudo-footless; virus detection;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2017009