Efficient CORDIC-based systolic architectures for the discrete Hartley transform

Presents two new linear systolic architectures for the 1D discrete Hartley transform (DHT). Both architectures exhibit several desired features such as regularity, modularity and high pipelineability, which make them amenable to VLSI hardware implementation. In addition, these new architectures use the CORDIC (Co-Ordinate Rotation DIgital Computer) algorithm as the basic function for each processing element, which has been shown to be an appealing approach to compute trigonometric functions. Combination of these two array processors to form a new fully pipelined mesh-connected systolic architecture for the 2D DHT is also addressed. This new architecture, which uses Horner´s rule and the symmetric property of the transform by folding the data either in the time domain or in the frequency domain, yield higher throughput with reduced hardware complexity compared with other existing ones for both the 1D and 2D case