Design and test generation of C-testable high-speed carry-free dividers

Presents a C-testable carry-free divider circuit design and its test generation. The divider circuit takes the dividend digits, in redundant binary form, and divisor digits, in binary form, as its inputs and produces the quotient and remainder digits, also in redundant binary form. The circuit is fully testable with a test set of 72 test patterns irrespective of its bit size. To generate the test patterns and the corresponding control signals easily, a graph labelling scheme is employed to derive a set of simple labels for the dividend, the divisor, the quotient, the remainder and the control signals