A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression

Author

Ming-Chiuan Su ; Wei-Zen Chen ; Pei-Si Wu ; Yu-Hsiang Chen ; Chao-Cheng Lee ; Shyh-Jye Jou

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

62

Issue

3

fYear

2015

fDate

Mar-15

Firstpage

743

Lastpage

751

Abstract

A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI_pp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps_rms. The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm² only. It dissipates 12.4 mW from 1 V supply.

Keywords

CMOS integrated circuits; clock and data recovery circuits; demultiplexing; interference suppression; jitter; passive optical networks; voltage-controlled oscillators; 10G-PON; CMOS; VCO; bit rate 10 Gbit/s; burst mode clock and data recovery circuit; data gating mode; demultiplexing; frequency 2 GHz; frequency 4 MHz; jitter suppression; passive optical network; phase tracking mode; size 55 nm; voltage 1 V; voltage 12.4 mV; Clocks; Computer architecture; Detectors; Jitter; Logic gates; Phase locked loops; Voltage-controlled oscillators; Burst-mode clock and data recovery (BMCDR); gated-VCO (GVCO); gigabit passive optical network (GPON); phase-locked loop (PLL);

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2014.2367573

Filename

6977996