• DocumentCode
    80302
  • Title

    Unified architecture for 2, 3, 4, 5, and 7-point DFTs based on Winograd Fourier transform algorithm

  • Author

    Qureshi, Fahad ; Garrido, Mario ; Gustafsson, Oscar

  • Author_Institution
    Linkoping Univ., Linköping, Sweden
  • Volume
    49
  • Issue
    5
  • fYear
    2013
  • fDate
    February 28 2013
  • Firstpage
    348
  • Lastpage
    349
  • Abstract
    A unified hardware architecture that can be reconfigured to calculate 2, 3, 4, 5, or 7-point DFTs is presented. The architecture is based on the Winograd Fourier transform algorithm and the complexity is equal to a 7-point DFT in terms of adders/subtractors and multipliers plus only seven multiplexers introduced to enable reconfigurability. The processing element finds potential use in memory-based FFTs, where non-power-of-two sizes are required such as in DMB-T.
  • Keywords
    discrete Fourier transforms; multiplexing equipment; DFT; DMB-T; Winograd Fourier transform algorithm; memory-based FFT; multiplexers; unified hardware architecture;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2012.0577
  • Filename
    6473951
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=80302