DocumentCode
803231
Title
Characterization of Total Safe Operating Area of Lateral DMOS Transistors
Author
Moens, Peter ; Van den Bosch, Geert
Volume
6
Issue
3
fYear
2006
Firstpage
349
Lastpage
357
Abstract
The total safe operating area (SOA) of LDMOS transistors is discussed. It is shown that the transistors are subjected to different kinds of stresses, yielding a combination of electrical and thermal degradation and/or failure modes. A methodology to build the total SOA for LDMOS transistors is highlighted and is experimentally verified on a 40-V LDMOS implemented in a
Keywords
MOSFET; hot carriers; power integrated circuits; 0.7 micron; 40 V; charge pumping; electrical degradation; energy capability; hot carriers; lateral LDMOS transistors; safe operating area; smart power technology; thermal degradation; transmission line pulsing; Auditory displays; Automotive engineering; Bipolar transistors; Breakdown voltage; Hot carriers; Power transmission lines; Semiconductor optical amplifiers; Temperature; Thermal degradation; Thermal stresses; Charge pumping (CP); LDMOS; energy capability; hot carriers; safe operating area (SOA); transmission line pulsing (TLP);
fLanguage
English
Journal_Title
Device and Materials Reliability, IEEE Transactions on
Publisher
ieee
ISSN
1530-4388
Type
jour
DOI
10.1109/TDMR.2006.882212
Filename
1717482
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