Delay-Reduction Technique for DWA Algorithms

Author

Jabbour, Chadi ; Fakhoury, Hussein ; Van Tam Nguyen ; Loumeau, Patrick

Author_Institution

LTCI, Inst. TELECOMTELECOM ParisTech, Paris, France

Volume

61

Issue

10

fYear

2014

fDate

Oct. 2014

Firstpage

733

Lastpage

737

Abstract

This brief presents a delay-reduction technique for data weighted averaging (DWA) algorithms. The proposed technique is based on quantizing the shift pointer of the DWA circuit, which leads to a complexity reduction of the shuffler and, consequently, to a delay reduction as well. Synthesis results in a 65-nm CMOS process show that the proposed technique reduces DWA delay below 100 ps for a 5-bit delta-sigma modulator. The proposed technique reduces the DWA in-band tones that arise as well, particularly for low input amplitudes.

Keywords

CMOS integrated circuits; delays; quantisation (signal); CMOS process; DWA Algorithm; DWA circuit; data weighted averaging algorithm; delay reduction technique; shift pointer quantization; shuffler reduction; wavelength 65 nm; Circuits and systems; Clocks; Delays; Linearity; Modulation; Noise; Quantization (signal); Analog-to-digital converter (ADC); data weighted averaging (DWA); delta??sigma ( $DeltaSigma$) modulator; digital-to-analog converter (DAC) linearization;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2014.2335437

Filename

6848829