Delay-Reduction Technique for DWA Algorithms

This brief presents a delay-reduction technique for data weighted averaging (DWA) algorithms. The proposed technique is based on quantizing the shift pointer of the DWA circuit, which leads to a complexity reduction of the shuffler and, consequently, to a delay reduction as well. Synthesis results in a 65-nm CMOS process show that the proposed technique reduces DWA delay below 100 ps for a 5-bit delta-sigma modulator. The proposed technique reduces the DWA in-band tones that arise as well, particularly for low input amplitudes.