A CMOS WCDMA/WLAN Digital Polar Transmitter With AM Replica Feedback Linearization

This paper presents a 65 nm CMOS digital polar transmitter with on-chip power amplifier (PA) for WCDMA and WLAN application. The proposed architecture is composed of a digital interpolation filter for up-sampling of the input amplitude-control word (ACW), a 9-bit switched-capacitor array for the digital polar modulation (DPM), and a 6-bit PA array to achieve the output power range for the target applications. A linearization technique is implemented by adaptively changing the PA bias voltage according to the RF envelope. To generate this bias voltage, the RF envelope of the PA input is extracted by a digital-to-analog converter (DAC) with the ACW signals as its input. A scaled replica of the PA, which only needs to operate at the Amplitude Modulation (AM) frequency, is employed to sense the RF envelope and to regulate the PA bias voltage with an analog feedback loop to minimize the distortion in the AM path. Even without amplitude pre-distortion, the transmitter system measures RMS-EVM of 2.83% and 4.07% for WCDMA and WLAN 54-Mb/s 64-QAM OFDM respectively while providing a peak output power of 20.4 dBm with PAE 32.3%.