DocumentCode
80351
Title
Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High- K Spacer for Low Power Applications
Author
Koley, Kalyan ; Dutta, Arin ; Syamal, Binit ; Saha, Samar K. ; Sarkar, Chandan K.
Author_Institution
Dept. of Electron. & Telecommun. Eng., Jadavpur Univ., Kolkata, India
Volume
60
Issue
1
fYear
2013
fDate
Jan. 2013
Firstpage
63
Lastpage
69
Abstract
This paper presents a systematic study of the subthreshold analog/RF performance for underlap double gate (UDG) NMOSFETs using high dielectric constant (k) spacers. The conventional UDG-NMOSFETs offer reduced short-channel effects along with improved subthreshold analog/RF performance at a cost of higher distributed channel resistance and low on current. In this paper, we show that these drawbacks can be alleviated effectively by using high-k spacers without any severe degradation in the subthreshold analog/RF performance. In order to show the improvement in the device performance, we have studied the effect of high-k spacers on different subthreshold analog figures of merit such as the transconductance, transconductance generation factor, output resistance, and the intrinsic gain for different values of k . Moreover, we have analyzed the RF performance as a function of intrinsic capacitance and resistance, transport delay, inductance, cutoff frequency, and the maximum oscillation frequency. In order to assess the gain bandwidth (GBW) product, the circuit implementation of the UDG-NMOSFETs with different high-k spacers was performed on a common source amplifier. Our results show an improvement in the GBW of about 38% for the devices with high- k spacers compared to its low- k counterpart.
Keywords
MOSFET; high-k dielectric thin films; low-power electronics; RF performance enhancement; common source amplifier; cutoff frequency; distributed channel resistance; gain bandwidth product; high-k spacers; intrinsic gain; short channel effects; subthreshold analog performance enhancement; transconductance generation factor; transport delay; underlap double gate NMOSFET; Capacitance; Doping; High K dielectric materials; Logic gates; Performance evaluation; Radio frequency; Resistance; Fringing capacitance; gate-to-source/drain resistances; spacer; subthreshold analog; symmetric underlap DG FET;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2012.2226724
Filename
6365259
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