DocumentCode
803560
Title
The nature of HT Vt shift in NROM memory transistors
Author
Fuks, David ; Kiv, Arnold ; Roizin, Yakov ; Gutman, Micha ; Avichail-Bibi, Rachel ; Maximova, Tatyana
Author_Institution
Dept. of Mater. Eng., Ben-Gurion Univ. of the Negev, Beer-Sheva, Israel
Volume
53
Issue
2
fYear
2006
Firstpage
304
Lastpage
313
Abstract
Physical mechanisms of Vt shift in NROM (micro FLASH) memory transistors microFLASH memory is the trademark of Tower Semiconductor Ltd. microFLASH is based on the NROM technology. NROM is the trademark of Saifun Semiconductor Ltd. after cycling are considered. Computer simulation is combined with analytical description of kinetics of "fast" Vt shift after cycling. The distinguishing feature of the developed model is its consistency with the positions of trapped charges obtained from charge pumping measurements and account for Coulomb correlation effects in the dynamics of injected charges in ONO. Accumulation of residual electrons and holes in the injection region and electrons trapped far from the drain is accounted in the model. Two main processes during the cycling determine the further HT Vt shift: the first one is caused by Coulomb repulsion of injected electrons, and another one is linked to the trapping and re-trapping of electrons. The dependence of "fast" Vt shift on the number of cycles is obtained and verified by experimental data. The approach can be used to predict the behavior of Vt during the long-term exploitation of memory devices that experienced up to 10 k program/erase cycles.
Keywords
charge injection; electron traps; flash memories; integrated circuit modelling; Coulomb correlation effects; Coulomb repulsion; NROM memory transistors; charge injection; charge pumping measurements; electron traps; memory devices; micro FLASH memory; nonvolatile memory transistors; reliability modeling; residual electrons; semiconductor memories; Charge carrier processes; Charge measurement; Charge pumps; Computer simulation; Current measurement; Electron traps; Kinetic theory; Poles and towers; Position measurement; Trademarks; NROM; nonvolatile memory (NVM) transistors; reliability modeling; semiconductor memories; trapping;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2005.862236
Filename
1580868
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