A 54-MHz CMOS programmable video signal processor for HDTV applications

Author

Joanblanq, Christophe ; Senn, Patrice ; Colaitis, Marie-Jean

Author_Institution

CNET, Meylan, France

Volume

25

Issue

3

fYear

1990

fDate

6/1/1990 12:00:00 AM

Firstpage

730

Lastpage

734

Abstract

A 54-MHz CMOS video processor with a systolic architecture suited for two-dimensional symmetric FIR (finite impulse response) filtering is reported. The circuit is a one-dimensional digital filter comprising a control part and an array of eight multiplication-accumulation cells. This processor is capable of handling 32 equivalent multiply-add operations in a sampling period as short as 18 ns. Devices can be cascaded to increase the order of the filter in both dimensions, up to 1024 stages with no truncation errors. It has been developed in a 1.2-μm CMOS technology, and it dissipates less than 500 mW at a 54-MHz clock frequency

Keywords

CMOS integrated circuits; digital filters; digital signal processing chips; high definition television; video signals; 1.2 micron; 54 MHz; CMOS programmable video signal processor; HDTV; equivalent multiply-add operations; multiplication-accumulation cells; one-dimensional digital filter; sampling period; systolic architecture; truncation errors; two-dimensional symmetric FIR; CMOS process; CMOS technology; Circuits; Digital filters; Filtering; Finite impulse response filter; Finite wordlength effects; HDTV; Sampling methods; Signal processing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.102667

Filename

102667