Title :
Pipelined architecture for fast CMOS buffer RAMs
Author :
Schmitt-Landsiedel, Doris ; Hoppe, Bernhard ; Neuendorf, Gerd ; Wurm, Maria ; Winnerl, Josef
Author_Institution :
Siemens AG, Munich, West Germany
fDate :
6/1/1990 12:00:00 AM
Abstract :
A novel pipeline architecture for CMOS static RAMs (SRAMs) that allows operation at very high clock rates is described. Basic requirements for achieving high speed are the implementation of a hierarchical architecture and a memory cell with separate READ and WRITE data lines. The access speed of hierarchically organized memory blocks was between 2.5 and 3.5 ns. The maximum operating frequency of a 16 K pipelined hierarchical SRAM (PHSRAM) is in the range of 300 MHz. The hierarchical architecture and a seven-transistor memory cell provide a circuit using digital swings all over. Key advantages of the full-swing static logic circuitry are robustness with respect to fabrication tolerances and a high-noise immunity. Moreover, the circuit can be reduced to finer structure sizes without any redesign, since there are no critical analog circuit parts
Keywords :
CMOS integrated circuits; buffer storage; integrated memory circuits; memory architecture; pipeline processing; random-access storage; 2.5 to 3.5 ns; CMOS buffer RAMs; PHSRAM; access speed; clock rates; digital swings; fabrication tolerances; full-swing static logic circuitry; hierarchical architecture; hierarchically organized memory blocks; high-noise immunity; memory cell; pipeline architecture; pipelined hierarchical SRAM; robustness; static RAMs; Analog circuits; Clocks; Fabrication; Frequency; Logic circuits; Memory architecture; Pipelines; Random access memory; Read-write memory; Robustness;
Journal_Title :
Solid-State Circuits, IEEE Journal of
