Quaternary logic circuits in 2-μm CMOS technology

Author

Shanbhag, Naresh R. ; Nagchoudhuri, Dipankar ; Siferd, Raymond E. ; Visweswaran, Gangaikond S.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., New Delhi, India

Volume

25

Issue

3

fYear

1990

fDate

6/1/1990 12:00:00 AM

Firstpage

790

Lastpage

799

Abstract

Novel quaternary logic circuits, designed in 2-μm CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-to-binary decoder, and the quaternary register are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra has been designed and fabricated. The prototype chip occupies an area of 4.84 mm², is timed with a 2.2-MHz clock, and consumes 93 mW of power

Keywords

CMOS integrated circuits; integrated logic circuits; invertors; logic arrays; many-valued logics; 2 micron; 2.2 MHz; 93 mW; Allen-Givone algebra; CMOS technology; binary-to-quaternary encoder; inverter; output voltage swing; power-delay product; pseudo-NMOS circuits; quaternary logic circuits; quaternary register; quaternary sequential/storage logic array; threshold detector circuits; tolerance estimations; CMOS logic circuits; CMOS technology; Circuit simulation; Decoding; Detectors; Inverters; Logic arrays; Logic circuits; Registers; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.102677

Filename

102677