Title :
Testing of multiple-output domino logic (MODL) CMOS circuits
Author :
Jha, Niraj K. ; Tong, Qiao
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fDate :
6/1/1990 12:00:00 AM
Abstract :
Techniques for testing MODL circuits are presented. It is shown that, due to the greater observability of MODL circuits, their test sets can be considerably small than those derived for the conventional domino CMOS circuits. Tests for faults are derived from a comprehensive fault model which includes stuck-at, stuck-open, and stuck-on faults. Test sets for MODL circuits are inherently robust in the presence of circuit delays and timing skews at the inputs. They are also well-protected against the charge distribution problem. It is thus concluded that MODL is an attractive CMOS logic technique
Keywords :
CMOS integrated circuits; fault location; integrated circuit testing; integrated logic circuits; logic testing; CMOS circuits; MODL; comprehensive fault model; multiple-output domino logic; observability; stuck-at faults; stuck-on faults; stuck-open faults; test sets; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Delay; Logic testing; Observability; Robustness; Semiconductor device modeling; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
