An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers

An MOS four-quadrant analog multiplier is described. It is based on the square-law dependence of the MOS-transistor drain current on the gate-to-source voltage in the saturation region. One input is applied to the gate directly while the other input is applied to the source through a source-follower buffer stage. The circuit is realized with only 12 MOS transistors and two resistors. The circuit has been fabricated using a metal-gate NMOS process which has separate p-wells to eliminate the substrate bias effect. The multiplier achieves less than 0.45% nonlinearity when the input voltage range is 40% of the supply voltages, and it achieves a -3-dB bandwidth of 30 MHz. The total harmonic distortion is less than 0.6%. The power consumption and chip size are 8 mW and 1.2 mm², respectively. The second-order effects for this type of multiplier are considered in detail