DocumentCode :
804029
Title :
Testing of zipper CMOS logic circuits
Author :
Tong, Qiao ; Jha, Niraj K.
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Volume :
25
Issue :
3
fYear :
1990
fDate :
6/1/1990 12:00:00 AM
Firstpage :
877
Lastpage :
880
Abstract :
Zipper CMOS is a dynamic CMOS circuit technique which also provides protection against instability and charge-sharing problems; this is achieved by using a special driver circuit. A method for testing of zipper CMOS circuits is presented. The testing is done with the help of a single stuck-at-fault test set derived from the gate-level model of the circuit in which the vectors have to be properly arranged and sometimes also repeated. This test set detects not just all detectable stuck-at faults but stuck-open and stuck-on faults as well. Very few stuck-open faults require two-pattern tests, and very few stuck-on faults need current monitoring. Thus, zipper CMOS circuits in particular and dynamic CMOS circuits in general enjoy a huge testability advantage over static CMOS circuits. Faults in the driver circuit are also considered
Keywords :
CMOS integrated circuits; driver circuits; fault location; integrated logic circuits; logic testing; charge-sharing problems; driver circuit; dynamic CMOS circuit technique; gate-level model; instability; stuck-at-fault test set; stuck-on faults; stuck-open faults; testability; zipper CMOS logic circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Driver circuits; Electrical fault detection; Fault detection; Logic testing; Protection; Semiconductor device modeling;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.102690
Filename :
102690
Link To Document :
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