A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration

Author

Daito, Mutsuo ; Matsui, Hirofumi ; Ueda, Masaya ; Iizuka, Kunihiko

Author_Institution

Adv. Technol. Dev. Labs., Sharp Corp., Nara

Volume

41

Issue

11

fYear

2006

Firstpage

2417

Lastpage

2423

Abstract

A new digital distortion calibration technique is demonstrated in a 14-bit 20-MS/s pipelined analog-to-digital converter (ADC). Calibration parameters are obtained in a way similar to conventional digital gain calibration. The prototype ADC has been fabricated in a 0.18-mum CMOS process and consumes 33.7 mW at 2.8 V. Using the proposed calibration method, a 15-dB improvement of the third-order harmonic rejection is achieved. The measured SNDR and SFDR are 71.6 and 82.3 dB, respectively

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; harmonic distortion; pipeline arithmetic; 0.18 micron; 14 bit; 2.8 V; 33.7 mW; CMOS analog integrated circuits; CMOS process; calibration parameters; digital distortion calibration; pipelined ADC; pipelined analog-to-digital converter; third-order harmonic rejection; Analog-digital conversion; Calibration; Capacitors; Feedback; Nonlinear distortion; Operational amplifiers; Prototypes; Sampling methods; Transfer functions; Voltage; Analog-to-digital converter (ADC); CMOS analog integrated circuits; calibration; distortion;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.882886

Filename

1717665